The present invention relates to a test insert and method for testing a microelectronic device. More particularly, the present invention provides a silicon insert for testing a chip-scale-packaged electronic device having an encapsulant-protrusion and plurality of outwardly-projecting-contacts of a ball-grid-array.
A well known package of the microelectronics industry for semiconductor die comprises a molded epoxy package having a plurality of conductive pins that electrically interface the semiconductor die. More recently, however, the industry has developed smaller packages and interface solutions that use solder balls arranged in an array disposed on a surface of an electronic device. The array of solder balls, known as a ball-grid-array or bump-grid-array (BGA), permit smaller distances between adjacent input/output lines and provide for greater input/output density and lower costs for these devices.
One exemplary, prior art, package is the flip-chip, which comprises, with reference to FIG. 1, a plurality of outwardly-projecting electrical contacts 14 placed directly upon a face 18 of a semiconductor die 12. The flip-chip 9 does not require bond wires between bond pads of the die and a lead frame of the more conventional pin-type packages (not shown). The solder balls or outwardly-projecting-contacts 14 of the flip-chip are preferably of the same size, for example, in the range of 0.3 to 0.4 millimeters in diameter, and placed in an array having a distance between adjacent balls of,.for example, about 1.5 mm. The advent of such BGA flip-chips led to the development of BGA test sockets.
Further referencing FIGS. 1-2, an exemplary prior art, BGA test socket 10 comprises a substrate 11 having a plurality of pockets 16 arranged in an array corresponding to the outwardly-projecting-contacts 14 of a flip-chip 9. A layer of conductive material 20 is formed and patterned over the substrate so as to provide conductive liners in pockets 16 and, conductive traces over the substrate in electrical communication with the pockets. Such prior art, BGA test socket 10 is able to temporarily seat a flip-chip, microelectronic device and electrically engage the outwardly-projecting contacts of its BGA interface. During testing of the flip-chip packaged microelectronic device, the test socket and the flip-chip are biased together with pockets 16 of the test socket engaged with the outwardly-projecting-contacts 14 of the flip-chip.
Recent trends of the semiconductor industry have led to development of smaller size semiconductor die. At the same time, the number of input/output lines required for the die have remained the same or have increased, thereby increasing their input/output densities. To accommodate these input/output density enhancements, the semiconductor manufacturers have developed alternative chip-scale packages.
One such alternative chip-scale-package is known as a xe2x80x9cglobbedxe2x80x9d chip-scale-package. With reference to FIGS. 3A, 3B, 3C, xe2x80x9cglobbedxe2x80x9d chip-scale-package 38 comprises a semiconductor die 12 mounted to an insulating support 32, also known as an interposer, which has an area about 1-2 times larger than die 12. Conductive lines 35 of interposer 32 electrically couple and re-route the small-size, fine-pitch, interposer pads 34 associated with die 12 to larger size, standard pitch, BGA contacts 14. The outwardly projecting contacts 14 of the interposer are designed in accordance, and for compliance, with conventional BGA standards.
Further referencing FIG. 3A, encapsulant protrusion 36 of globbed chip-scale-package 38, is disposed between and amongst a plurality of the outwardly protruding contacts 14 of the chip-scale-package. Encapsulant protrusion 36 comprises a material, e.g., non-conductive epoxy, suitable for enclosing interposer opening 31. Encapsulant protrusion 36 protects and encases bond-wires 30 which bond-wires bond-out and electrically couple terminals 29 of die 12 to conductive pads 34 of interposer 32. Encapsulant protrusion 36 of globbed chip-scale-package 38, with reference to FIG. 3C, usually has a height h2 beyond the face of interposer 32 less than the height h1 of the outwardly projecting contacts 14.
Prior art, BGA test inserts, for example the insert as shown in FIG. 1, may not provide reliable testing of the globbed chip-scale-packaged, microelectronic devices. When using such prior art, test insert to test globbed chip-scale-packaged, microelectronic devices, a region of upper surface 19 of the test insert may contact the encapsulant protrusion 36 of the globbed chip-scale-packaged microelectronic device, so as to interfere and prevent engagement of its outwardly projecting-contacts 14 with respective pockets 16 of the test insert 10.
What is needed is a BGA test socket for a globbed chip-scale-packaged, microelectronic device, which socket overcomes some of the problems of the prior art. What is also needed is a test insert capable of providing full and reliable, temporary electrical engagement with such microelectronic device. What is also needed is a method of reliably testing a globbed chip-scale-packaged, microelectronic device.
The present invention relates to the formation of an insert for engaging a microelectronic device having outwardly projecting contact bumps. The insert may be known by such terms as a receptacle, a BGA socket, an interconnect, a BGA test receiver, or silicon insert. The present invention recognizes and overcomes problems of the prior art caused by an encapsulant projection of a globbed chip-scale-packaged microelectronic device interfering with the interconnection of the insert with the outwardly projecting contacts of the chip-scale-packaged microelectronic device.
In accordance with one embodiment of the present invention, an insert is formed for seating and testing a chip-scale-packaged microelectronic device having a plurality of outwardly projecting contacts and a protrusion. The substrate is formed with walls that define a plurality of pockets configured to seat and engage the outwardly projecting contacts of the chip-scale-package. Other walls of the substrate define a recess configured to receive with clearance the encapsulant protrusion of the chip-scale-package when the outwardly projecting contacts are seated in the plurality of pockets.
In accordance with one aspect of this exemplary embodiment, the recess has a perimeter encompassing an area greater that that of a plurality of the pockets.
In accordance with another aspect of the exemplary embodiment, the recess of the insert is formed simultaneously with the pockets and of equal depth.
In accordance with another exemplary embodiment of the present invention, an insert comprises a substrate having walls that define a plurality of pockets that are configured to receive the outwardly projecting contacts of a microelectronic device. Other walls of the substrate may define vias that pass through the substrate and are in communication with associated pockets of the plurality. Conductive material fills the vias and lines a pocket connected to the via.
These and other features of the present invention will become more fully apparent in the following description and independent claims, or may be learned by the practice of the invention as set forth hereinafter.